This disclosure relates in general to electronic design automation (EDA) and, more specifically logic synthesis of a circuit involving retiming.
Retiming is a logic synthesis technique that structurally relocates registers in a design in a manner that preservers output functionality. It can be applied to minimize or meet a constraint on a worst-case combinational delay and/or to minimize the number of registers, merely by way of example. The original registers may have reset signals that restore them to specific logic values, and for the retimed circuit to be functionality equivalent, it should have the same behavior when a reset is asserted. This can often be achieved by selecting a corresponding set of reset values for the retimed registers. For some retimed circuits, however, no such set may exist; either the circuit structure or retiming transformation needs to be altered.
Merely by way of example, FIG. 1A provides one example of a portion of a circuit with no corresponding set of reset values that exist when the portion is retimed. In this example, registers R1 and R2 have initial reset values initialized to logic one. When this circuit is retimed with relocated registers R′x and R′y, no set of reset values exist such that the retimed circuit has the same behavior when a reset is asserted. This may be referred to as an unjustifiable retiming.
There are several known approaches to handling an unjustifiable retiming. The problem may be how to accomplish this with minimal increase in area and worst-case timing.
One approach to handling an unjustifiable retiming is to constrain the mobility of the registers so that the result is justifiable and then to recompute retiming with constraints on the original circuit. This may not require modifying any combinational logic. Another approach is to unmap the reset functionality from the sequential state element; this may involve explicit reset circuitry. This may not be possible in all circuit styles, but if it can be done, the registers can then be retimed independently of the combinational reset logic.
A limitation with the first approach is that the constraint may limit the ability of retiming to improve the quality of the result. Timing-critical registers may be constrained from any backward movement at all, in which case these path delays can not be improved. Furthermore, the generation of optimal constraints may be a computationally intractable problem, in which case over-conservatism (and possible further loss in quality) may be necessary.
A limitation with the second approach may be that the additional combinational reset logic lengthens the path at the input of each backward-retimed register by at least one gate. These gates may also contribute additional area. These additions may compromise the total quality-of-results benefit from retiming the circuit.
There is thus a need for methods, apparatuses, and systems that may be used to create justifiable circuits as part of a retiming.